Techniques disclosed herein relate to semiconductor device fabrication.
Modern semiconductor devices such as, for example, integrated circuit (IC) devices or chips, may be manufactured by processing a semiconductor carrier such as a wafer. Integrated circuits may include a plurality of layers, e.g. one or more semiconducting, insulating, and/or conducting layers, which may be stacked one over the other. Having accurate overlay (alignment) of an upper layer to a lower layer is beneficial to device performance. Alignment marks have been used for alignment, for example, when aligning lithographically defined layers by means of a stepper or scanner.
Scribe lane alignment marks are typically used in the fabrication of integrated circuitry to precisely align the substrates with respect to reticles which are used to pattern the substrates. Typically at least two of such marks are placed within a scribe lane area of a substrate, often between integrated circuit die areas. Scribe lanes are also known as scribe lines. Alignment marks can include a plurality of raised and/or lowered or buried features for which a stepper/scanner can optically search to determine and/or modify x-y alignment of the substrate for subsequent processing. Individual spaced features within an alignment mark can be spaced rectangles, although any configuration can be used.